The present invention pertains to signal track reduction in complex array processors and more particularly to improving signal quality by transferring a signal from the periphery to the interior of a VLSI circuit (very large scale integrated circuit).
Shrinking geometries in VLSI wafer fabrication technology have caused transistor counts to increase. Improvements in manufacturing yield of wafer fabrication technology have caused sizes to grow. Signal leads are typically connected to VLSI circuits by bonding pads at the periphery of the circuit. These signals are then transferred from the bonding pads to the internal operational portions of the circuit by metal traces, leads, or tracks on the integrated circuit substrate. Since die sizes are growing larger, the ability to rapidly transfer electrical signals without losing signal quality from the periphery of a VLSI circuit to the interior is inhibited. This problem is exacerbated by the use of finer and finer line widths or tracks on the integrated circuit. As a result, propagation delays that were once considered insignificant through these tracks are now delayed substantially and synchronization of such signals is an important consideration in the design of VLSI circuitry. This is because long, thin tracks have high resistance and capacitance which increases losses and degrades the signal rise and fall times.
It is an advantage of the present invention to provide an arrangement for transferring widely distributed signals such as clock signals, power, and ground signals rapidly, without significant propagation delays, with minimal signal degradation and provide the ability to use wider tracks for the distribution of signals.